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      "content": "@Tholin Sorry, but I don't think my Mac has enough umph to run a design that size. If you get partial logs/reports you can send them to me. \n\nI've seen long run times when the fill/cap cells aren't parallelized before comparison. May not be relevant.",
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      "content": "Thanks, I'll check later today.",
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      "content": "@Tholin the setup file for `gf180mcuD` provides for parallel reduction of `fillcap` cells but not `decap` cells. If you are creating a new standard cell library for `gf180mcu_as_sc_mcu7t3v3` then I suggest you either,\n1. rename the `decap` cells to `fillcap` to match the `5v0` libraries or\n2. modify the netgen setup file to reduce parallel `decap` cells.",
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      "content": "I did this and its still taking forever. There are also still warnings in the log that I don\u201dt see with the 5V SCL",
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      "content": "The first is due to yosys adding buffers to increase capacitance on nets (I think). The outputs are unconnected - normal.\nThe second is netgen output saying that it was told to ignore a parameter that did not exist on a device - also normal.\n\nIf you could send me the partial log, I can take a look at it.",
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